1. Field of the Invention
The present invention relates to a data buffer and method, and in particular, to a data buffer and method for using same that interfaces input/output buffers in a multi-state programmable memory.
2. Background of the Related Art
Generally, programmable memory devices such as a mass storage flash memory have less than 8 (i.e., 1 byte) input/output pins, and internally have dozens of sense amplifiers. The input/output pins transmit data by being synchronized to a clock signal, which has a clock cycle being dozens of nanoseconds (nsecs). The input/output buffer continuously transmits a predetermined volume of data according to the clock cycle or clock signal speed. However, a time for the sense amplifier to read data from flash memory cells is dozens of nsecs, and a time for the sense amplifier to write the data to the flash memory cells is hundreds of nsecs-dozens of microseconds (.mu.secs). Thus, both the data reading and the data writing speed are slower than the data processing speed of the input/output pins. Accordingly, a data buffer is required to buffer differences of volume of data and of data transmission speed during the data reading and the data writing processes.
A capacity of the data buffer should be equal to a minimum volume of data that the data pins continuously receive. Generally, the minimum volume of received data is equal to data in a row of a memory. An access time of the data buffer should be faster than a data transmission time of the input/output buffer. The data buffer serves as an embedded memory provided in the programmable memory and mainly employs a latch array or a CMOS SRAM array, etc. therefor.
FIG. 1 is a circuit diagram of a related art data buffer for a multi-state programmable memory. As shown in FIG. 1, the related art data buffer for the multi-state programmable memory is provided with a cell array 1 having a plurality of columns, a plurality of sense amplifiers 2 that are respectively connected to a corresponding one of the columns of the cell array 1 and a plurality of data registers 3 each having a couple of inverters, for example INV3-1A, INV3-1B. The inverters INV3-1A and INV3-1B have inputs and outputs respectively connected to each other to latch a corresponding one of the sense amplifiers 2. An input/output buffer 4 is connected to each output of the data registers 3.
As described above, the related art data buffer has various disadvantages. When the construction of the sense amplifiers is simple, each column of the programmable memory can be connected to a corresponding one of the sense amplifiers 2. Thus, each of the sense amplifiers 2 is connected to a latch, which is a corresponding one of the data registers 3, to serve as the data buffer. However, if the size of each of the sense amplifiers is so large that each column can not be connected to the sense amplifiers, it is very difficult or impossible to array the latches. Also, the data buffer for the multi-state programmable memory should process data of at least 2 bits from the sense amplifiers. However, the related art data register has a problem processing the two or more bit data in a multi-state programmable memory.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.